1. Field of the Invention
The present invention relates to a delay circuit and, more particularly, to a programmable delay circuit excellent in the linearity of delay characteristics and adapted for use in an IC tester or the like.
2. Description of the Prior Art
A conventional example will be described below with reference to the accompanying drawings.
FIG. 1 is a circuit diagram showing the basic configuration of a known programmable delay circuit. In this diagram, reference numerals 5a and 5b denote input terminals fed with input signals to be delayed, such as clock pulse signals. For example, input signals having mutually opposite phases are supplied to the input terminals 5a and 5b. Denoted by 1 is a delay circuit comprising series-connected N stages G1 to Gn (where N.gtoreq.2), wherein input electrodes (bases) of a pair of differential amplifying transistors P11 and P12 are connected between the first delay stage G1 and the second delay stage G2 of the delay circuit 1, and output electrodes (collectors) of such transistors constitute a buffer 2 while being connected respectively to common output terminals VOUT and VOUTB via cascode-connected transistors Pb1 and Pb2. Denoted by R1a and R2a are load resistors connected to a power terminal Vref (e.g. ground) and common output terminals VOUT and VOUTB respectively. There are also included a current switch 3 consisting of transistors P1 to Pn-1, and a common current source 4 having a current value Iref. The differential amplifying transistors P11, P12 and the transistor P1 of the current switch 3 constitute a first differential amplifier D1. Meanwhile, differential amplifying transistors P21, P22 connected between the second and third delay stages G2, G3 and the transistor P2 of the current switch 3 constitute a second differential amplifier D2; and differential amplifying transistors Pn-11, Pn-12 connected between the third and Nth delay stages G3, Gn and the transistor Pn-1 of the current switch 3 constitute an (N-1)th differential amplifier Dn-1. There is further included a control circuit 5 for selectively controlling the current switch 3 in such a manner as to control one of the transistors P1 to Pn-1 of the current switch 3 in response to k-bit digital signals d.sub.1 to d.sub.k.
Now a description will be given on the operation performed in the above circuit configuration.
In FIG. 1, if the transistor P1 of the current switch 3 is selected in response to digital signals d.sub.1 to d.sub.k of the control circuit 5, the transistor P1 is turned on to supply a current Iref of the common current source 4 to the differential amplifying transistors P11 and P12 of the first differential amplifier D1, so that the signals fed to the input terminals 5a and 5b are delivered to the first delay stage G1, whose outputs are amplified by the first differential amplifier D1 and then are supplied to the common output terminals VOUT and VOUTB via the buffer 2. Similarly, if the transistor P2 of the current switch 3 is selected, the transistor P2 is turned on to supply the current Iref of the common current source 4 to the differential amplifying transistors P21 and P22 of the second differential amplifier D2, so that the signals fed to the input terminals 5a and 5b are delivered to the second delay stage D2, whose outputs are amplified by the second differential amplifier D2 and then are supplied to the common output terminals VOUT and VOUTB via the buffer 2. Thus, the outputs of the n-1 delay stages G1 through Gn-1 can be selectively outputted by controlling the current switch 3 for the plural differential amplifiers D1 through Dn-1 in response to the control signals A1 through An-1 obtained from the control circuit 5. And in selecting any of the transistors P1 through Pn-1 of the current switch 3 for the plural differential amplifiers D1 through Dn-1, the delay caused by any of the differential amplifiers D1 through Dn-1 is maintained constant and the fixed delay time is shortened to consequently achieve satisfactory linearity of the delay characteristics. In addition, the power consumption can be reduced due to the use of a single common current source 4.
Furthermore, since the cascode-connected buffer 2 is provided between the outputs of the differential amplifiers D1 to Dn-1 and the common output terminals VOUT and VOUTB, the apparent output capacitance of each of the differential amplifying transistors P11 to Pn-12 is rendered smaller to consequently realize a faster operation. And the delay time can further be prolonged by additionally providing an unshown another differential amplifier at the output of the Nth delay stage Gn.
FIG. 2 is a concrete circuit diagram of the conventional programmable delay circuit shown in FIG. 1. A description will now be given below with regard to this circuit diagram.
In FIG. 2, the component elements corresponding to those used in FIG. 1 are denoted by the same reference numerals, and a detailed explanation thereof is omitted.
In this diagram, the delay circuit 1 of FIG. 1 comprises eight stages, i.e., a 1st delay stage G1 to an 8th delay stage D8, each of which consists of an emitter follower circuit and a differential amplifier. Transistors P1 to P8 constituting a current switch 3 for a 1st differential amplifier D1 to an 8th differential amplifier D8 are controlled by control signals A1 to A8 obtained from an unshown control circuit. If the delay time of each delay stage is 100 psec in this conventional example of FIG. 2, the total delay time is changeable in a range from 100 to 800 psec (e.g., 10 nsec when 2.sup.n =128), so that the same effect as in the circuit of FIG. 1 is rendered expectable. In the example of FIG. 2 where input pulse signals are transmitted in push-pull phase opposition, the duty ratio of the input pulse signals can be maintained constant until the output.
In the delay circuit of the constitution mentioned above, the delay caused by each differential amplifier is constant regardless of selection of any current switch for the plural differential amplifiers, thereby enhancing the linearity of the delay characteristics. And another advantage is attainable with respect to reduction of the power consumption due to employment of a single common current source. However, since each delay stage consists of an emitter follower circuit and a differential amplifier, the settable delay time in each delay stage is limited to 100 psec or so, hence raising a problem that a control operation is impossible relative to any short delay time on the order of picosecond for example.